(a) Field of the Invention
The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electrical conductivity, and minimizing electrical signal delay without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.
(b) Description of the Related Art
Electronic package technology is very broad, and includes various system manufacturing technologies including all the processes from a semiconductor device to a final product. In particular, with the rapid development of electronic products, electronic package technology is a very important for achieving compactness, lightness, and high performance of devices.
Electronic package technology is also a very important technology for determining performance, size, price, reliability, etc., of final electronic products. In particular, in recent electronic products pursuing high electrical performance, subminiature/high density, low power, multi-function, ultrahigh speed signal processing, and permanent reliability, the subminiature package parts are needed as essential parts for computers, information communication devices, mobile communication devices, premium home appliances, etc.
An example of a representative technology of three-dimensionally stacking semiconductor devices including chips to connect the semiconductor devices or mount the semiconductor devices on a substrate may include wire bonding technology, flip chip technology, and through silicon via (TSV) technology.
Wire bonding technology, which is a technology of attaching and connecting a wire to a metal pad of a connection part using an ultrasonic tool, is inexpensive in view of manufacturing costs but has a limitation in connecting fine pitches and high-density electrodes due to the bonding between the wire and the metal pad, and cannot be used for parts requiring ultrahigh speed signal processing due to an increase in parasitic inductance according to an increase in the length of the signal line for electrically connecting between the connection parts.
The flip chip technology is largely divided into two, i.e., a solder flip chip using solder and a non-solder flip chip not using solder. The solder flip chip has problems in that production cost is increased due to a very complicated connection process such as solder flux application, chip/substrate alignment, solder bump reflow, flux removal, underfill filling, curing, etc. Therefore, recently, the non-solder flip chip technology has gained a large amount of interest in order to reduce the number of complicated processes.
A representative technology of the non-solder flip chip is a flip chip technology using an anisotropic conductive film (ACA). The flip chip technology using the existing ACA includes a process in which an ACA material is applied or temporarily bonded to substrates and the chips and the substrates are aligned, and heat and pressure are finally applied thereto to complete the flip chip package. However, the process has a long process time in forming a film or applying or temporarily bonding the ACA material to each substrate.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.